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www.fairchildsemi.com rev. 1.1.0 3/27/03 pentium is a registered trademark of intel corporation. athlon is a registered trademark of amd. programmable active droop is a trademark of fairchild semiconductor. block diagram 22 vid0 11 10 14 13 17 16 24 - + osc digital control power good 5-bit dac vid1 vid2 vid3 vid4 1234 5 +12v pwrgd - + enable/ss vo agnd 7 droop/e* 18 6 +12v 15 5v reg bypass 23 r t +12v +12v 12 8 9 21 +12v digital control - + - + - + 19 ilim 20 boot a boot b gnda current limit uvl o f an5093 t wo phase interleaved synchronous buck converter for vrm 9.x applications features programmable output from 1.10v to 1.85v in 25mv steps using an integrated 5-bit dac ? wo interleaved synchronous phases for maximum performance 100nsec transient response time built-in current sharing between phases remote sense programmable active droop ? (voltage positioning) programmable switching frequency from 100khz to 1mhz per phase adaptive delay gate switching integrated high-current gate drivers integrated power good, ov, uv, enable/soft start functions drives n-channel mosfets operation optimized for 12v operation high ef?iency mode (e*) at light load ? v ercurrent protection using mosfet sensing 24 pin tssop package applications ? o wer supply for pentium ? iv ? o wer supply for athlon ? vrm for pentium iv processor programmable step-down power supply description the fan5093 is a synchronous two-phase dc-dc controller ic which provides a highly accurate, programmable output v oltage for vrm 9.x processors. two interleaved synchro- nous buck regulator phases with built-in current sharing operate 180?out of phase to provide the fast transient response needed to satisfy high current applications while minimizing external components. the fan5093 features programmable active droop ? for transient response with minimum output capacitance. it has integrated high-current gate drivers, with adaptive delay gate switching, eliminating the need for external drive devices. the fan5093 uses a 5-bit d/a converter to program the output voltage from 1.10v to 1.85v in 25mv steps with an accuracy of 1%. the fan5093 uses a high level of integra- tion to deliver load currents in excess of 50a from a 12v source with minimal external circuitry. the fan5093 also offers integrated functions including power good, output enable/soft start, under-voltage lock- out, over-voltage protection, and adjustable current limiting with independent current sense on each phase. it is available in a 24 pin tssop package.
fan5093 product specification 2 rev. 1.1.0 3/27/03 pin assignments pin de?itions pin number pin name pin function description 1-5 vid0-4 voltage identification code inputs. open collector/ttl compatible inputs will program the output voltage over the ranges specified in table 1. internally pulled- up. 6 bypass 5v rail. bypass this pin with a 0.1 f ceramic capacitor to agnd. 7 agnd analog ground. return path for low power analog circuitry. this pin should be connected to a low impedance system ground plane to minimize ground loops. 8 ldrvb low side fet driver for b. connect this pin to the gate of an n-channel mosfet for synchronous operation. the trace from this pin to the mosfet gate should optimally be <0.5 " . 9 pgndb power ground b. return pin for high currents flowing in low-side mosfet. connect directly to low-side mosfet source. 10 swb high side driver source and low side driver drain switching node b. gate drive return for high side mosfet, and negative input for low-side mosfet current sense. 11 hdrvb high side fet driver b. connect this pin to the gate of an n-channel mosfet. the trace from this pin to the mosfet gate should optimally be <0.5 " . 12 bootb bootstrap b. input supply for high-side mosfet. 13 boota bootstrap a. input supply for high-side mosfet. 14 hdrva high side fet driver a. connect this pin to the gate of an n-channel mosfet. the trace from this pin to the mosfet gate should optimally be <0.5 " . 15 swa high side driver source and low side driver drain switching node a. gate drive return for high side mosfet, and negative input for low-side mosfet current sense. 16 pgnda power ground a. return pin for high currents flowing in low-side mosfet. connect directly to low-side mosfet source. 17 ldrva low side fet driver for a. connect this pin to the gate of an n-channel mosfet for synchronous operation. the trace from this pin to the mosfet gate should optimally be <0.5 " . 18 vcc vcc. internal ic supply. connect to system 12v supply, and decouple with a 10 ? resistor and 1 f ceramic capacitor. 19 pwrgd power good flag. an open collector output that will be logic low if the output voltage is less than 350mv less than the nominal output voltage setpoint. power good is prevented from going low until the output voltage is out of spec for 500?ec. fan5093 vid0 vid1 vid2 vid3 vid4 agnd bypass ldrvb pgndb swb hdrvb bootb vfb rt enable/ss droop/e* ilim pwrgd vcc ldrva p gnda swa hdrva boota 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
product specification fan5093 rev. 1.1.0 3/27/03 3 absolute maximum ratings (absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied.) thermal ratings recommended operating conditions (see figure 2) 20 ilim current limit. a resistor from this pin to ground sets the over current trip level. 21 droop/e* droop control/energy star mode control. a resistor from this pin to ground sets the amount of droop by controlling the gain of the current sense amplifier. when this pin is pulled high to bypass, the phase a drivers are turned off for energy-star operation. 22 enable/ss output enable/softstart. a logic low on this pin will disable the output. an 10? internal current source allows for open collector control. this pin also doubles as soft start. 23 rt frequency set. a resistor from this pin to ground sets the switching frequency. 24 vfb voltage feedback. connect to the desired regulation point at the output of the converter. p arameter min. max. unit supply voltage vcc 15 v supply voltages boot to pgnd 24 v boot to sw 24 v voltage identification code inputs, vid0-vid4 6 v vfb, enable/ss, pwrgd, droop/e* 6 v swa, swb to agnd (<1?) -3 15 v pgnda, pgndb to agnd -0.5 0.5 v gate drive current, peak pulse 3 a junction temperature, t j -55 150 c storage temperature -65 150 c p arameter min. typ. max. unit lead soldering temperature, 10 seconds 300 c power dissipation, p d 650 mw thermal resistance junction-to-case, jc 16 c/w thremal resistance junction-to-ambient, ja 84 c/w p arameter conditions min. max. units output driver supply, boota, b 16 22 v ambient operating temperature 0 70 c supply voltage v cc 10.8 13.2 v pin number pin name pin function description
fan5093 product specification 4 rev. 1.1.0 3/27/03 electrical speci?ations (v cc = 12v, vid = [01111] = 1.475v, and t a = +25? using circuit in figure 2, unless otherwise noted.) the ? denotes speci?ations which apply over the full operating temperature range. notes: 1. as measured at the converter? vfb sense point. for motherboard applications, the pcb layout should exhibit no more than 0.5m ? trace resistance between the converter? output capacitors and the cpu. remote sensing should be used for optimal performance. 2. using the vfb pin for remote sensing of the converter? output at the load, the converter will be in compliance with vrm 9.x specification. p arameter conditions min. typ. max. units input supply uvlo hysteresis 0.5 v 12v uvlo rising edge ? 8.5 9.5 10.3 v 12v supply current pwm output open 20 ma internal voltage regulator bypass voltage 4.75 5 5.25 v bypass capacitor 100 nf vref and dac output voltage see table 1 ? 1.100 1.850 v initial voltage setpoint 1 i load = 0a, vid = [01111] 1.460 1.475 1.490 v output temperature drift t a = 0 to 70? 5 mv line regulation v cc = 11.4v to 12.6v ? 130 ? droop 2 i load = 69a, r droop = 13.3k ? 56 mv programmable droop range 0 1.25 m ? response time ? v out = 10mv 100 nsec current mismatch r ds,on (a) = r ds,on (b), i load = 69a, droop = 1m ? 5% vid inputs input low current, vid pins v vid = 0.4v -60 ? vid v ih 2.0 v vid v il 0.8 v oscillator oscillator frequency rt = 54.9k ? ? 440 500 560 khz oscillator range rt = 137.5k ? to 13.75 k ? 200 2000 khz maximum duty cycle rt = 137.5k ? 90 % minimum ldrv on-time rt = 13.75k ? 330 nsec gate drive gate drive on-resistance sink & source 1.0 ? output driver rise & fall time see figure 1, c l = 3000pf 20 nsec enable/soft start soft start current 10 ? enable threshold on off 1.0 0.4 v po wer good pwrgd threshold logic low, v vid ?v pwrgd ? 85 88 92 %v out pwrgd output voltage i sink = 4ma 0.4 v pwrgd delay high low 500 ?ec o vp and otp output overvoltage detect ? 2.1 2.2 2.3 v over temperature shutdown 130 140 150 ? over temperature hysteresis 40 ?
product specification fan5093 rev. 1.1.0 3/27/03 5 gate drive test circuit figure 1. output drive timing diagram ta b le 1. output voltage programming codes note: 1. 0 = vid pin is tied to gnd. 1 = vid pin is pulled up to 5v. vid4 vid3 vid2 vid1 vid0 v out to cpu 11111off 11110 1.100v 11101 1.125v 11100 1.150v 11011 1.175v 11010 1.200v 11001 1.225v 11000 1.250v 10111 1.275v 10110 1.300v 10101 1.325v 10100 1.350v 10011 1.375v 10010 1.400v 10001 1.425v 10000 1.450v 01111 1.475v 01110 1.500v 01101 1.525v 01100 1.550v 01011 1.575v 01010 1.600v 01001 1.625v 01000 1.650v 00111 1.675v 00110 1.700v 00101 1.725v 00100 1.750v 00011 1.775v 00010 1.800v 00001 1.825v 00000 1.850v t r t f t dt t dt hdrv ldrv 2v 2v 10% 3000pf v out 2v 90% 90% 2.5v 10%
fan5093 product specification 6 rev. 1.1.0 3/27/03 t ypical operating characteristics (v cc = 12v, v out = 1.475v, and t a = +25? using circuit in figure 2, unless otherwise noted.) efficiency vs. output current load current (a) efficiency (%) high-side gate drives, rise / fall time high-side gate drives, e*-mode adaptive gate delay high-side gate drives, normal operation low-side gate drives, rise / fall time ch1: hdrvb ch2: hdrva 40a load ch1: hdrvb 40a load ch1: hdrvb ch2: hdrva 10a load ch1: hdrvb ch2: ldrvb 40a load ch1: ldrvb 40a load 70 75 80 85 90 010203 040 50 6 07080 2 phase mode e* mode
product specification fan5093 rev. 1.1.0 3/27/03 7 t ypical operating characteristics (continued) dynamic vid change current limit current sharing, 70a load output ripple, 70a load current sharing, 30a load droop vs. r droop ch1: i l1 (5a/div) ch2: i l2 (5a/div) ch1: iin ch2: vout ch1: i l1 (5a/div) ch2: i l2 (5a/div) ch1: v out (1.475v-1.575v) ch2: vid2 40a load rdroop (k ? ) droop (mv/a) (m ? ) 0.00 0.50 1.00 1.50 2.00 2.50 3.00 010 51520253 03540 r t = 49.9k r t = 61.9k
fan5093 product specification 8 rev. 1.1.0 3/27/03 t ypical operating characteristics (continued) start-up, 40a load load transient, 12-52a power-down, 40a load load transient, 0-40a ch1: iout (20a/div) ch2: vout ch1: iout (20a/div) ch2: vout ch1: vout ch2: vin ch1: vout ch2: vin v out temperature variation temperature ( c) 1.501 1.500 1.499 1.498 1.497 1.496 1.495 1.494 0257 0 100 v ou t (v) closed loop response, 40a load frequency (hz) gain (db) phase margin (deg.) gain phase margin -10 0 10 20 30 40 50 100 1000 10000 100000 0 30 60 90 120 150 180
product specification fan5093 rev. 1.1.0 3/27/03 9 application circuit figure 2. application circuit for 70a vrm 9.x desktop application ta b le 2. fan5093 application bill of materials for figure 2 reference qty description manufacturer / number u1 1 ic, pwm, fan5093 fairchild fan5093 q1-8 8 nfet, 30v, 50a, 9m ? fairchild fdd6696 d1, 2, 3 3 dios, 40v, 500ma fairchild mbr0540 l1, 2 2 ind, 850nh, 30a, 0.9m ? inter-technical scta5022a-r85m l3 opt ind, 750nh, 20a, 3.5m ? inter-technical sc4015-r75m r1-4, 9 5 4.7 ? , 5% r5-8 4 2.2 ? , 5% r10 1 10 ? , 5% r11 1 10k, 5% r12 1 75.0k, 1% r13 1 13.3k, 1% r14 1 56.2k, 1% c1-6 6 1.0?, 25v, 10%, x7r c7-10 4 0.1?, 16v, 10%, x7r cin 4 1500?, 16v, 20%,12m ? , aluminum electrolytic rubycon 16mbz1500m cout 8 2200?, 6.3v, 20%, 12m ? , aluminum electrolytic rubycon 6.3mbz2200m +12 v c3 r11 r6 + cout c2 q5 l2 c7 d3 r2 vid 3 q8 r5 vid4 q2 q3 vi n r1 vid 0 r10 c1 vcor e r3 r13 c9 q6 q1 c6 r4 r12 r7 q7 r14 vid 1 + cin vi n fan5093 u1 8 11 1 2 3 4 5 24 20 14 22 6 12 9 13 17 7 18 15 10 16 23 21 19 ldrvb hdrvb vid0 vid1 vid2 vid3 vid4 vfb il im hdrva enable/ss bypass bootb pgnd b boota ld rva agnd vcc swa swb pgnda rt droop/e* pwrgd r9 c8 l1 r8 +5 v l3 c4 q4 c5 vid 2 c10 d2 d1
fan5093 product specification 10 rev. 1.1.0 3/27/03 application information operation the fan5093 controller the fan5093 is a programmable synchronous two-phase dc-dc controller ic. when designed with the appropriate e xternal components, the fan5093 can be con?ured to deliver more than 50a of output current, for vrm 9.x applications. the fan5093 functions as a ?ed frequency pwm step down regulator, with a high ef?iency mode (e*) at light load. main control loop refer to the fan5093 block diagram on page 1. the f an5093 consists of two interleaved synchronous buck con- v erters, implemented with summing-mode control. each phase has its own current feedback, and there is a common v oltage feedback. the two buck converters controlled by the fan5093 are interleaved, that is, they run 180 out of phase. this mini- mizes the rms input ripple current, minimizing the number of input capacitors required. it also doubles the effective switching frequency, improving transient response. the fan5093 implements ?umming mode control? which is different from both classical voltage-mode and current- mode control. it provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads and external components. no external compen- sation is required. the control loop of the regulator contains two main sections: the analog control block and the digital control block. the analog section consists of signal conditioning ampli?rs feeding into a comparator which provides the input to the digital control block. the signal conditioning section accepts inputs from a current sensor and a voltage sensor, with the v oltage sensor being common to both phases, and the current sensor separate for each. the voltage sensor ampli?s the difference between the vfb signal and the reference voltage from the dac and presents the output to each of the two comparators. the current control path for each phase takes the difference between its pgnd and sw pins when the low- side mosfet is on, reproducing the voltage across the mosfet and thus the input current; it presents the resulting signal to the same input of its summing ampli?r, adding its signal to the voltage ampli?rs with a certain gain. these two signals are thus summed together. this sum is then pre- sented to a comparator looking at the oscillator ramp, which provides the main pwm control signal to the digital control block. the oscillator ramps are 180 out of phase with each other, so that the two phases are on alternately. the digital control block takes the analog comparator input to provide the appropriate pulses to the hdrv and ldrv output pins for each phase. these outputs control the external power mosfets. response time the fan5093 utilizes leading-edge, not trailing-edge control. conventional trailing-edge control turns on the high-side mosfet at a clock signal, and then turns it off when the error ampli?r output voltage is equal to the ramp v oltage. as a result, the response time of a trailing-edge converter can be as long as the off-time of the high-side driver, nearly an entire switching period. the fan5093s leading-edge control turns the high-side mosfet on when the error ampli?r output voltage is equal to the ramp volt- age, and turns it off at the clock signal. as a result, when a transient occurs, the fan5093 responds immediately by turning on the high-side mosfet. response time is set by the internal propagation delays, typically 100nsec. in worst case, the response time is set by the minimum on-time of the low-side mosfet, 330nsec. oscillator the fan5093 oscillator section runs at a frequency deter- mined by a resistor from the rt pin to ground according to the formula the oscillator generates two internal sawtooth ramps, each at one-half the oscillator frequency, and running 180 out of phase with each other. these ramps cause the turn-on time of the two phases to be phased apart. the oscillator frequency of the fan5093 can be programmed from 200khz to 2mhz with each phase running at 100khz to 1mhz, respectively. selection of a frequency will depend on various system performance criteria, with higher frequency resulting in smaller components but typically lower ef?iency. remote voltage sense the fan5093 has true remote voltage sense capability, elim- inating errors due to trace resistance. to utilize remote sense, the vfb and agnd pins should be connected as a kelvin trace pair to the point of regulation, such as the processor pins. the converter will maintain the voltage in regulation at that point. care is required in layout of these grounds; see the layout guidelines in this datasheet. high current output drivers the fan5093 contains four high current output drivers that utilize mosfets in a push-pull con?uration. the drivers for the high-side mosfets use the boot pin for input power and the sw pin for return. the drivers for the low-side mosfets use the vcc pin for input power and the pgnd pin for return. typically, the boot pin will use a charge pump as shown in figure 2. note that the boot and vcc pins are separated from the chips internal power and ground, bypass and agnd, for switching noise immunity. r t ? () 27.5e9 fhz () ------------------- =
product specification fan5093 rev. 1.1.0 3/27/03 11 adaptive delay gate drive the fan5093 embodies an advanced design that ensures minimum mosfet transition times while eliminating shoot-through current. it senses the state of the mosfets and adjusts the gate drive adaptively to ensure that they are never on simultaneously. when the high-side mosfet turns off, the voltage on its source begins to fall. when the voltage there reaches approximately 2.5v, the low-side mosfets g ate drive is applied. when the low-side mosfet turns off, the voltage at the ldrv pin is sensed. when it drops below approximately 2v, the high-side mosfets gate drive is applied. maximum duty cycle in order to ensure that the current-sensing and charge- pumping work, the fan5093 guarantees that the low-side mosfet will be on a certain portion of each period. for low frequencies, this occurs as a maximum duty cycle of approxi- mately 90%. thus at 250khz, with a period of 4?ec, the low-side will be on at least 4?ec ?10% = 400nsec. at higher frequencies, this time might fall so low as to be ineffective. the fan5093 guarantees a minimum low-side on-time of approximately 330nsec, regardless of duty cycle. current sensing the fan5093 has two independent current sensors, one for each phase. current sensing is accomplished by measuring the source-to-drain voltage of the low-side mosfet during its on-time. each phase has its own power ground pin, to per- mit the phases to be placed in different locations without affecting measurement accuracy. for best results, it is impor- tant to connect the pgnd and sw pins for each phase as a k elvin trace pair directly to the source and drain, respec- tively, of the appropriate low-side mosfet. care is required in the layout of these grounds; see the layout guidelines in this datasheet. current sharing the two independent current sensors of the fan5093 operate with their independent current control loops to guarantee that the two phases each deliver half of the total output current. the only mismatch between the two phases occurs if there is a mismatch between the r ds,on of the low-side mosfets. light load ef?iency at light load, the fan5093 uses a number of techniques to improve ef?iency. because a synchronous buck converter is two quadrant, able to both source and sink current, during light load the inductor current will ?w away from the out- put and towards the input during a portion of the switching c ycle. this reverse current ? w is detected by the f an5093 as a positive voltage appearing on the low-side mosfet during its on-time. when reverse current ?w is detected, the low-side mosfet is turned off for the rest of the cycle, and the current instead ?ws through the body diode of the high-side mosfet, returning the power to the source. this technique substantially enhances light load ef?iency. short circuit current characteristics (ilim pin) the fan5093 short circuit current characteristic includes a function that protects the dc-dc converter from damage in the event of a short circuit. the short circuit limit is set with the r s resistor, as given by the formula with i sc the desired output current limit, rt the oscillator resistor and r ds,on one phases low-side mosfets on resistance. remember to make the r s large enough to include the effects of initial tolerance and temperature varia- tion on the mosfets r ds,on . important note! the oscillator frequency must be selected before selecting the current limit resistor, because the value of rt is used in the calculation of r s . when an overcurrent is detected, the high-side mosfets are turned off, and the low-side mosfets are turned on, and they remain in this state until the measured current through the low-side mosfet has returned to zero amps. after reaching zero, the f an5093 re-soft-starts, ensuring that it can also safely turn on into a short. a limitation on the current sense circuit is that i sc ?r ds,on must be less that 375mv. to ensure correct operation, use i sc ?r ds,on 300mv; between 300mv and 375mv, there will be some non-linearity in the short-circuit current not accounted for in the equation. as an example, consider the typical characteristic of the dc-dc converter circuit with two fdp6670al low-side mosfets (r ds = 6.5m ? maximum at 25 c ?1.2 at 75 c = 7.8m ? each, or 3.9m ? total) in each phase, rt = 42.1k ? (600khz oscillator) and a 50k ? r s . the converter exhibits a normal load regulation characteris- tic until the voltage across the mosfets exceeds the inter- nal short circuit threshold of 50k ? /(3.9m ? 41.2k ? 6.66) = 47a. [note that this current limit level can be as high as 50k ? /(3.5m ? ?41.2k ? ?6.66) = 52a, if the mosfets have typical r ds,on rather than maximum, and are at 25 c.] at this point, the internal comparator trips and signals the controller to leave on the low-side mosfets and keep off the high-side mosfets. the inductor current decreases, and power is not applied again until the inductor current reaches 0a and the converter attempts to re-softstart. e*-mode in addition, further enhancement in ef?iency can be obtained by putting the fan5093 into e*-mode. when the droop pin is pulled to the 5v bypass voltage, the a? phase of the fan5093 is completly turned off, reducing in half the amount of gate charge power being consumed. e*-mode can be implemented with the circuit shown in figure 3. r s ? () i sc r ds on , r t 3.33 ? ? ? =
fan5093 product specification 12 rev. 1.1.0 3/27/03 figure 3. implementing e*-mode control note: the charge pump for the hidrvs should be based on the ??phase of the fan5093, since the a?phase is off in e*-mode. internal voltage reference the reference included in the fan5093 is a precision band- g ap voltage reference. its internal resistors are precisely trimmed to provide a near zero temperature coef?ient (tc). based on the reference is the output from an integrated 5-bit da c. the dac monitors the 5 voltage identi?ation pins, vid0-4, and scales the reference voltage from 1.100v to 1.850v in 25mv steps. bypass reference the internal logic of the fan5093 runs on 5v. to permit the ic to run with 12v only, it produces 5v internally with a linear regulator, whose output is present on the bypass pin. this pin should be bypassed with a 100nf capacitor for noise suppression. the bypass pin should not have any external load attached to it. dynamic voltage adjustment the f an5093 can have its output voltage dynamically adjusted to accommodate low power modes. the designer must ensure that the transitions on the vid lines all occur simultaneously (within less than 500 nsec) to avoid false codes generating undesired output voltages. the power good ?g tracks the vid codes, but has a 500?ec delay transitioning from high to low; this is long enough to ensure that there will not be any glitches during dynamic voltage adjustment. po wer good (pwrgd) the fan5093 power good function is designed in accor- dance with the pentium iv dc-dc converter speci?ations and provides a continuous voltage monitor on the vfb pin. the circuit compares the vfb signal to the vref voltage and outputs an active-low interrupt signal to the cpu should the power supply voltage deviate more than -12% of its nom- inal setpoint. the power good ?g provides no control func- tions to the fan5093. output enable/soft start (enable/ss) the fan5093 will accept an open collector/ttl signal for controlling the output voltage. the low state disables the output voltage. when disabled, the pwrgd output is in the low state. even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nf) to soft- start the switching. a softstart capacitor may be approxi- mately chosen by the formula: where: t d is the delay time before the output starts to ramp t r is the ramp time of the output c ss = softstart cap v out = nominal output voltage however, c must be 100nf. programmable active droop the fan5093 features programmable active droop: as the output current increases, the output voltage drops propor- tionately an amount that can be programmed with an exter- nal resistor. this feature is offered in order to allow maximum headroom for transient response of the converter. the current is sensed losslessly by measuring the voltage across the low-side mosfet during its on time. consult the section on current sensing for details. the droop is adjusted by the droop resistor changing the gain of the current loop. note that this method makes the droop dependent on the temperature and initial tolerance of the mosfet, and the droop must be calculated taking account of these tolerances. given a maximum output current, the amount of droop can be programmed with a resistor to ground on the droop pin, according to the formula with v droop the desired droop voltage, rt the oscillator resistor, i max the output current at which the droop is desired, and r ds, on the on-state resistance of one phases low-side mosfet. important note! the oscillator frequency must be selected before selecting the droop resistor, because the value of r t is used in the calculation of r droop . over-voltage protection the fan5093 constantly monitors the output voltage for protection against over-voltage conditions. if the voltage at fan5098, pin 6 (bypass) fan5098, pin 21 (droop, e*) 2n3906 hi=e*mode 2n3904 1k 10k 10k 10k r droop t d c ss 10 a -------------- 1.7 0.9074 v out ? + () 2.5 --------------------------------------------------------- - ? = t r c ss 10 a -------------- v out 0.9 ? v in ---------------------------- ? = r droop ? () v droop r t ? i max r ds on , ? ------------------------------------ - =
product specification fan5093 rev. 1.1.0 3/27/03 13 the vfb pin exceeds 2.2v, an over-voltage condition is assumed and the fan5093 latches on the external low-side mosfet and latches off the high-side mosfet. the dc-dc converter returns to normal operation only after v cc has been recycled. over temperature protection if the f an5093 die temperature exceeds approximately 150 c, the ic shuts itself off. it remains off until the temper- ature has dropped approximately 25 c, at which time it resumes normal operation. component selection mosfet selection this application requires n-channel enhancement mode field effect transistors. desired characteristics are as follows: ? ow drain-source on-resistance, ? ds,on < 10m ? (lower is better); ? o wer package with low thermal resistance; drain-source voltage rating > 15v; ? ow gate charge, especially for higher frequency operation. f or the low-side mosfet, the on-resistance (r ds,on ) is the primary parameter for selection. because of the small duty c ycle of the high-side, the on-resistance determines the power dissipation in the low-side mosfet and therefore signi?antly affects the ef?iency of the dc-dc converter. f or high current applications, it may be necessary to use two mosfets in parallel for the low-side for each phase. f or the high-side mosfet, the gate charge is as important as the on-resistance, especially with a 12v input and with higher switching frequencies. this is because the speed of the transition greatly affects the power dissipation. it may be a good trade-off to select a mosfet with a somewhat higher r ds,on , if by so doing a much smaller gate charge is av ailable. for high current applications, it may be necessary to use two mosfets in parallel for the high-side for each phase. at the fan5093s highest operating frequencies, it may be necessary to limit the total gate charge of both the high-side and low-side mosfets together, to avert excess power dis- sipation in the ic. f or details and a spreadsheet on mosfet selection, refer to applications bulletin ab-8. gate resistors use of a gate resistor on every mosfet is mandatory. the g ate resistor prevents high-frequency oscillations caused by the trace inductance ringing with the mosfet gate capacitance. the gate resistors should be located physically as close to the mosfet gate as possible. the gate resistor also limits the power dissipation inside the ic, which could otherwise be a limiting factor on the switch- ing frequency. it may thus carry signi?ant power, especially at higher frequencies. as an example: the fdb7045l has a maximum gate charge of 70nc at 5v, and an input capaci- tance of 5.4nf. the total energy used in powering the gate during one cycle is the energy needed to get it up to 5v, plus the energy to get it up to 12v: this power is dissipated every cycle, and is divided between the internal resistance of the fan5093 gate driver and the g ate resistor. thus, and each gate resistor thus requires a 1/4w resistor to ensure w orst case power dissipation. inductor selection choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. a smaller inductor produces greater ripple while producing better transient response. in any case, the minimum induc- tance is determined by the allowable ripple. the ?st order equation (close approximation) for minimum inductance for a two-phase converter is: where: v in = input power supply v out = output voltage f = dc/dc converter switching frequency esr = equivalent series resistance of all output capacitors in parallel vripple = maximum peak to peak output ripple voltage b udget. schottky diode selection the application circuit of figure 2 shows a schottky diode, d1 (d2 respectively), one in each phase. they are used as free-wheeling diodes to ensure that the body-diodes in the low-side mosfets do not conduct when the upper mosfet is turning off and the lower mosfets are turning on. it is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades ef?iency, and so the schottky provides a shunt path for the current. since this time duration is extremely short, being minimized by the adaptive gate delay, the selection criterion for the diode is that the forward voltage of eqv 1 2 -- - c + ? v 2 ? 7 0nc 5v 1 2 -- - + ? 5.4nf 12v 5v () 2 ? == 48 2nj = p rgate efr gate ? ? r gate r internal + () ------------------------------------------------ - 48 2nj 300khz ? == 4.7 ? 4.7 ? 0.5 ? + -------------------------------- - 13 1mw = ? l min v in 2v ? out f ---------------------------------- - v out v in ----------- esr v ripple ----------------- ? ? =
fan5093 product specification 14 rev. 1.1.0 3/27/03 the schottky at the output current should be less than the for- w ard v oltage of the mosfets body diode. power capability is not a criterion for this device, as its dissipation is very small. output filter capacitors the output bulk capacitors of a converter help determine its output ripple voltage and its transient response. it has already been seen in the section on selecting an inductor that the esr helps set the minimum inductance. for most con- v erters, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the esr and not the capacitance v alue. that is, in order to achieve the necessary esr to meet the transient and ripple requirements, the capacitance value required is already very large. the most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low esr. the only type of aluminum capacitor used should be those that have an esr rated at 100khz. consult application bulletin ab-14 for detailed information on output capacitor selection. f or higher frequency applications, particularly those running the fan5093 oscillator at >1mhz, oscon or ceramic capaci- tors may be considered. they have much smaller esr than comparable electrolytics, but also much smaller capacitance. the output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1? and 0.01? are recommended values. input filter the dc-dc converter design may include an input inductor between the system main supply and the converter input as shown in figure 2. this inductor serves to isolate the main supply from the noise in the switching portion of the dc-dc converter, and to limit the inrush current into the input capac- itors during power up. a value of 1.3? is recommended. it is necessary to have some low esr capacitors at the input to the converter. these capacitors deliver current when the high side mosfet switches on. because of the interleaving, the number of such capacitors required is greatly reduced from that required for a single-phase buck converter. figure 2 shows 3 x 1500 f, b ut the exact number required will vary with the output voltage and current, according to the formula for the two phase fan5093, where dc is the duty cycle, dc = vout / vin. capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to ?d out the ripple current rating at the expected opera- tional temperature. for details on the design of an input ?ter, refer to applications bulletin ab-16. figure 4. input filter design considerations and component selection additional information on design and component selection may be found in fairchilds application note 59. pcb layout guidelines placement of the mosfets relative to the fan5093 is critical. place the mosfets such that the trace length of the hidrv and lodrv pins of the fan5093 to the fet g ates is minimized. a long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the fet. this noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very dif?ult to suppress. in general, all of the noisy switching lines should be kept aw ay from the quiet analog section of the fan5093. that is, traces that connect to pins 8-17 (lodrv, hidrv, pgnd and boot) should be kept far away from the traces that connect to pins 1 through 7, and pins 18-24. place the 0.1? decoupling capacitors as close to the f an5093 pins as possible. extra lead length on these reduces their ability to suppress noise. each power and ground pin should have its own via to the appropriate plane. this helps provide isolation between pins. place the mosfets, inductor, and schottky of a given phase as close together as possible for the same reasons as in the ?st bullet above. place the input bulk capacitors as close to the drains of the high side mosfets as possible. in addition, placement of a 0.1 f decoupling cap right on the drain of each high side mosfet helps to suppress some of the high frequency switching noise on the input of the dc-dc converter. place the output bulk capacitors as close to the cpu as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. additional space between the output capacitors and the cpu will allow the parasitic resistance of the board traces to degrade the dc-dc converters performance under severe load transient conditions, causing higher voltage deviation. for more detailed information regarding capacitor placement, refer to application bulletin ab-5. ? pc board layout checklist is available from fairchild applications. ask for application bulletin ab-11. i rms i out 2 -------- - 2dc 4dc 2 = l3 +12v 1000 f, 16v electrolytic vin
product specification fan5093 rev. 1.1.0 3/27/03 15 pc motherboard sample layout and gerber file a reference design for motherboard implementation of the f an5093 along with the pcad layout gerber ?e and silk screen can be obtained through your local fairchild repre- sentative. f an5093 evaluation board f airchild provides an evaluation board to verify the system level performance of the fan5093. it serves as a guide to performance expectations when using the supplied external components and pcb layout. please contact your local f airchild representative for an evaluation board. additional information f or additional information contact your local fairchild representative.
fan5093 product specification 16 rev. 1.1.0 3/27/03 mechanical dimensions ?24 lead tssop a .047 1.20 symbol inches min. max. min. max. millimeters notes a1 .002 .006 0.05 0.15 .012 0.30 b .007 0.19 c .004 .008 0.09 0.20 e .169 .177 4.30 4.50 .018 .030 0.45 0.75 .026 bsc 0.65 bsc e .252 bsc 6.40 bsc h l 0 8 0 8 3 5 2 2 n24 24 ccc .004 0.10 d .303 .316 7.70 7.90 notes: 1. 2. 3. 4. 5. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e" do not include mold flash. mold flash or protrusions shall not exceed .006 inch (0.15mm). "l" is the length of terminal for soldering to a substrate. terminal numbers are shown for reference only. symbol "n" is the maximum number of terminals. h e a d e b a1 ?c ccc c lead coplanarity seating plane l c
fan5093 product specification 3/27/03 0.0m 005 stock#ds30005093 ? 2003 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. ordering information product number description package FAN5093MTC vrm 9.x dc-dc controller 24 pin tssop FAN5093MTCx vrm 9.x dc-dc controller 24 pin tssop in tape and reel

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